Codex FPGA/SoC FPGA 多角色且基于证据工程工作流：逐拍 RTL、CDC/RDC、STA、官方 IP、三厂商原生脚本、单一实现者与独立签核。
An interactive git diff for VLSI timing signoff; visually compares two STA reports before and after a design change, instantly showing which paths sped up, slowed down, or newly violated timing.
ASIC Physical Design of ChipTop using Cadence Innovus | Complete RTL-to-GDSII Flow | Floorplanning | Macro Placement | CTS | Routing | Timing Closure | TCL Automation
Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.
End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.
Multi-seed Quartus timing CI for MiSTer FPGA cores: compares a PR against master across many fitter seeds, posts reviewer-ready stats, and hunts for seeds that meet timing.
UART Safety Controller ASIC implementation project demonstrating RTL synthesis, SKY130 technology mapping, multi-corner static timing analysis (TT/SS/FF), timing closure, CDC/RDC review, and implementation readiness for ASIC physical design.
Two-stage 32-bit ALU with RTL verification, flow scaffolding, and a sanitized timing/CTS case study.
SAR16 数字后端签核：RTL、时序约束与收敛证据
Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2
Electrical repair of a placed design: repeaters along each net's Steiner tree and driver resizing, wherever a wire is too long or a capacitance, fanout or transition limit is broken.
Turn AI-assisted RTL into a reviewable FPGA engineering flow with 13 focused roles, live contracts, and evidence-triggered P&R.
Post-route hold-fix ECO: insert series delay cells on hold-violating capture pins to close hold timing.
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