[AdaWorldAPI]

Summary

This probe compares two ways of computing an exact signed 9-bit (-255..=255) dot product using only the existing ndarray::simd facade. Both read the same input per operand: 64 u8 magnitudes and one u64 polarity plane.

The arithmetic contract

Sign is a routing decision. Multiplication is an exact decomposition. Accumulation is a fold.

For each lane pair:

p        = m_a * m_b                  exact, always fits u16
negative = polarity_a XOR polarity_b
acc      = acc - p  if negative, else acc + p

Magnitudes are never negated. The polarity XOR only chooses which side of the fold each product joins. The two candidates are different facade compositions of this same contract: neither is more exact than the other, and they produce the same results.

• A: U8 × U8 × sign × mul_add. The whole product m_a * m_b is formed in f32 after widening (A' forms it in u16 with mullo), then added to the positive or the negative sum according to the XOR plane.
• B: U8 × I8 byte-dot. The product is decomposed the way long multiplication (schriftliche Multiplikation) decomposes it:
  • low7 = m_b & 0x7F;
  • top = m_b ^ low7, read as a signed byte, so it is 0 or -128;
  • therefore m_b = low7 - top and m_a * m_b = m_a * low7 - m_a * top;
  • for example, 255 × 255 = 32,385 + 32,640 = 65,025;
  • four dot4_u8_i8_add_masked calls run per block, with the XOR plane as the mask.

No production code changed. The work is examples/u9_head_to_head/{kernels,main}.rs, tests/u9_head_to_head.rs, and the report .claude/knowledge/turbovec9-u9-head-to-head.md.

Result

B is faster in every row, including the symmetric per-block row. Figures are ns per 64 values, data in L1, ranges over 3 runs.

row	AVX-512 VNNI	AVX-512, no VNNI	AVX2
plain u8 × i8 byte-dot	1.89 – 1.94	1.97 – 2.02	2.13 – 2.16
A' end-to-end	7.78 – 7.80	7.77 – 7.81	75 – 82
B end-to-end	3.03 – 3.05	5.67 – 6.22	9.9 – 10.4
A scan	6.95 – 7.14	6.97 – 7.14	70 – 77
B scan	2.69 – 2.77	4.81 – 4.95	9.0 – 9.2

The streamed and arithmetic-only rows are in the report.

A's cost comes from how this composition lowers through the current facade: widening u8 → u16 → f32, and on AVX2, U8x64::mask_blend. It is not a property of U8 × U8 multiplication. Other lowerings of A were not explored. On the AVX-512 builds, the disassembly shows no shuffle, permute, pack, extract or insert in B, in the baselines, or in the flushes. On AVX2 that is not true: LLVM emits 4 vpshufb inside the facade's masked byte-dot (dot4_u8_i8_add_masked), which it uses to spread the bytes of the keep mask. That instruction comes from the facade's own AVX2 code, not from this probe, and was not changed here.

Exactness

Both candidates are bit-exact (no rounding, saturation or wrap) under two conditions:

• the operands are among the 511 numeric values (never-touched is refused by check, which callers run before the kernel);
• the running total fits in i64, which holds up to about 2.2 × 10¹² worst-case blocks.

The bounds at each stage:

candidate	per-lane bound	flush
A	256 × 65,025 = 16,646,400, below 2²⁴	every 256 blocks
B	16,384 × 130,560 = 2,139,095,040, below i32::MAX	every 16,384 blocks

Tests, all checked against one independent i64 oracle:

• all 511 × 511 pairs;
• full mixed blocks;
• worst-case runs past both flush bounds, where every byte is 255, so top = -128 and the byte-dot would saturate if it could;
• never-touched refused in either operand;
• the split itself for all 256 magnitudes through the kernel's own prepare_b. low7 XOR top gives back the original byte, low7 - top gives back its value, and changing a polarity bit changes only the routing plane, never the bytes.

The tests pass on native, v4, v3, AVX (qemu), v2 (qemu), aarch64 (qemu) and nightly-simd. I broke each of twelve checks on purpose, and every time the tests failed. CI runs this test file only in its x86 test jobs. The other tiers were run locally.

Not proven here:

• exactness beyond the i64 total;
• other lowerings of A;
• CI coverage of every tier;
• anything about Codebook512 decoding.

Facade gap (recorded, not filled)

The facade has no U8x64 → I8x64 bit view. As a stand-in, bits_as_i8 stores the 64 bytes and loads them back as signed; its cost is inside B's operand preparation. It is not added to the facade because it crosses between u8 and i8.

TurboVec-U9 handoff

The report keeps Arithmetic511 (DR512: 511 values plus the never-touched sentinel) separate from Codebook512 (512 distinct IDs). An exact arithmetic kernel does not make Lloyd-Max512 decoding lossless. #387 measured 329 distinct values after snapping, and the lookup cost is reported.

https://claude.ai/code/session_01XAqKMMjKnig6MXTd41Lf2v

---

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