[AdaWorldAPI]

Summary

This probe checks #390's facade word in a real consumer. It adds one new candidate, AccE5, to examples/u9_abacus/anchor.rs. E5 keeps E's split |b| = low7 + 128·bit7 and the two masked low7 byte-dots, and computes the anchor term in two persistent U64x8::sum8_u8_add_masked accumulators, one per sign. These accumulators are reduced only at flush, once every B_FLUSH_BLOCKS = 16,384 blocks. E3, E4, Esum and B are unchanged. Nothing changes in the facade, the backends, the codecs or the storage format.

Answer to the final question: the vertical accumulator makes the anchor cheaper than B's fourth byte-dot only where the byte-dot is not a single instruction.

Tier	Verdict	Complete consumer vs B (ns per 64 values)
AVX-512 without VNNI	ADOPT-LAB	L1 end-to-end 5.14 – 5.30 vs 5.67 – 7.50 (about 9% faster over 8 runs, ranges disjoint); arithmetic 4.47 vs 5.08, lower in all 8 paired runs; scan 4.67 vs 4.83; streamed end-to-end lower in every paired run
AVX-512 VNNI	REFUSE as a B replacement	L1 end-to-end 3.55 – 3.95 vs 2.92 – 3.25; scan 3.31 vs 2.62 – 3.05; streamed end-to-end tie
AVX2	REFUSE as a B replacement	L1 end-to-end 12.2 vs 10.0; streamed end-to-end 40 vs 27 – 32

Overall verdict: DEFER as a general replacement for B. E5 is the best of the four E variants on every tier, and the first E variant that beats B anywhere.

Why

These are the steady-state loop bodies, taken from out-of-line copies of the loops:

• VNNI: mask expansion.
  • B runs in 18 instructions. Both of B's byte-dots per sign reuse one zero-masked copy of a, so the fourth dot costs one vpdpbusd.
  • E5 runs in 23 instructions. Its anchor mask is sign AND bit7, which differs from the low7 mask, so it needs its own zero-masked move, a vpsadbw and a vpaddq per sign.
  • Other causes are ruled out: there are 0 spills, the accumulator chains are independent, and streamed is a tie, so memory traffic doesn't decide it either.
• AVX-512 without VNNI: E5 wins. Each masked byte-dot is emulated with about 10 instructions. B's loop is 40 instructions, E5's is 36. Neither spills.
• AVX2: mask construction. The facade word builds its keep mask in registers on every call, which costs 8 vpshufb and 16 vpmuludq per block. E5's loop is 185 instructions, B's is 154. Both spill, because the AVX2 types are array-backed.
• Flush is cheaper for E5 (27.6 vs 48.5 ns on VNNI). LLVM fuses the two anchor reductions into one vpsubq followed by one horizontal reduction. Amortized over the flush interval, every candidate's flush costs under 0.003 ns per 64 values.

Bounds

• A low7 lane gains at most 129,540 per block, which totals 2,122,383,360 per flush, below i32::MAX.
• An anchor lane gains at most 2,040 per block, or 33.4M per flush. The 8 lanes plus the << 7 stay at most 3.4e10, inside i64.

Correctness

5 new tests in tests/u9_abacus.rs, against #388's i64 oracle and against B:

• all 511 × 511 numeric pairs, end to end and as a scan;
• mixed full blocks; the test asserts that mixed signs and bit-7 magnitudes are present;
• all-255 runs past three flush bounds, with all four sign mixes;
• exactly one anchor reduction per flush, read from AccE5::reductions;
• touched zero scores 0, and never-touched is refused.

The tests pass on native, v4, v3, AVX (qemu), v2 (qemu), aarch64 (qemu) and nightly-simd. scripts/wasm-parity.sh and scripts/neon-parity.sh pass. Clippy with -D warnings and rustfmt are clean, and the facet-stride guard reports nothing on the added lines.

Six disable runs, each red:

• X1: bit-7 gating lost;
• X2: polarity inverted;
• X3: reconstruction shifted by << 6;
• X4: anchor reduction missing;
• X5: anchors not reset at flush;
• X6: premature reduction.

X6 is caught only by the reduction counter. An early reduction is a cost defect, not a wrong result, so every exactness test stays green.

Full tables, including E3, E4 and Esum, the streamed and scan rows, and the disassembly, are in .claude/knowledge/u9-e5-probe.md. This closes fruit U1 from #392.

Not in this PR

• No production kernel, no new facade word, no codec change, no TurboVec integration.
• No NEON or wasm timings, since qemu and node timings are not meaningful.
• No mask-sharing E5 variant: it would need a new facade word.

---

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