Engineering executive and architect. Twenty years building systems and the organizations that ship them in payments, healthcare, enterprise SaaS, defense, and AI infrastructure.
📍 Richardson, TX · 🎓 MS ECE, Purdue
I operate at both ends of the stack and treat that as one job, not two.
⬇️ Down the stack — RF and VLSI (5.25 GHz LNA, 6G receiver in 45nm CMOS), compute-in-memory macro characterization, CUDA kernels (GEMM, Tensor Core WMMA, Flash Attention), embedded systems and RTOS, CAN/CANOpen, ROS2.
⬆️ Up the stack — carrier-grade platform architecture, IoT gateways, SIP/VoIP, data center networks, LLM routing and orchestration, semantic layers over fragmented enterprise estates.
🧪 Where I use them — 6T SRAM compute-in-memory macro characterization (dual-Vmin at 0.55–0.65V, mixed-Vt HVT-storage / LVT-access, 58% energy reduction at 0.65V) · 5.25 GHz LNA · 45nm CMOS 6G receiver front-end · RF conformance across GPS L1/L5, WiFi, and BLE · high-speed mixed-signal design · IC/MEMS fabrication.
🤖 ML & accelerators
🏗️ Platform & data
☁️ Infrastructure
🦾 Embedded & edge
⚡ The unifying thread: I care about what the abstraction is hiding. Usually it's a transistor.