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riscv: add multikernel architecture skeleton #37
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,48 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| #ifndef _ASM_RISCV_MULTIKERNEL_H | ||
| #define _ASM_RISCV_MULTIKERNEL_H | ||
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| #ifndef __ASSEMBLY__ | ||
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| #include <linux/errno.h> | ||
| #include <linux/sizes.h> | ||
| #include <linux/types.h> | ||
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| #include <asm/page.h> | ||
| #include <asm/smp.h> | ||
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| /* | ||
| * Hart IDs are sparse firmware identifiers and may exceed NR_CPUS. Keep | ||
| * them as values and always translate through the architecture CPU maps. | ||
| */ | ||
| static inline u64 arch_cpu_physical_id(int cpu) | ||
| { | ||
| return cpuid_to_hartid_map(cpu); | ||
| } | ||
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| static inline int arch_cpu_from_physical_id(u64 hartid) | ||
| { | ||
| if (hartid == INVALID_HARTID) | ||
| return -ENOENT; | ||
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| return riscv_hartid_to_cpuid(hartid); | ||
| } | ||
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| /* | ||
| * The RISC-V spawn path will use one page for its context, up to 64 KiB | ||
| * for the generated DTB, and one page for the fence.i entry stub. SBI HSM | ||
| * starts a hart in the existing address space, so no trampoline page tables | ||
| * are needed. | ||
| */ | ||
| #define MK_CTRL_BLOCK_SIZE (SZ_64K + 2 * PAGE_SIZE) | ||
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| /* | ||
| * Architecture-private spawn state is added with the SBI HSM and Image | ||
| * loader support. The compile-only skeleton intentionally has none. | ||
| */ | ||
| struct mk_instance_arch { | ||
| }; | ||
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| #endif /* !__ASSEMBLY__ */ | ||
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| #endif /* _ASM_RISCV_MULTIKERNEL_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,3 @@ | ||
| # SPDX-License-Identifier: GPL-2.0-only | ||
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| obj-y += spawn.o |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| // SPDX-License-Identifier: GPL-2.0-only | ||
| /* | ||
| * RISC-V multikernel architecture interface skeleton. | ||
| * | ||
| * The SBI HSM spawn and park implementation is added by the follow-up | ||
| * architecture patches. Until then, operations which would change CPU | ||
| * ownership fail explicitly instead of pretending that a hart moved. | ||
| */ | ||
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| #include <linux/errno.h> | ||
| #include <linux/kernel.h> | ||
| #include <linux/kexec.h> | ||
| #include <linux/multikernel.h> | ||
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| void mk_arch_send_ipi(mk_phys_cpu_t phys_cpu) | ||
| { | ||
| pr_warn_once("RISC-V multikernel IPI support is not implemented\n"); | ||
| } | ||
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| void mk_arch_register_cpu(mk_phys_cpu_t phys_id) | ||
| { | ||
| /* RISC-V CPU topology already records possible harts. */ | ||
| } | ||
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| void __noreturn mk_enter_pool_state(void *info) | ||
| { | ||
| /* Unreachable while CONFIG_ARCH_HAS_MK_POOL_STATE is disabled. */ | ||
| panic("RISC-V multikernel pool parking is not implemented"); | ||
| } | ||
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| int mk_arch_register_force_stop(void) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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| void mk_force_stop_cpu(mk_phys_cpu_t phys_cpu) | ||
| { | ||
| pr_warn_once("RISC-V multikernel force-stop is not implemented\n"); | ||
| } | ||
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| int mk_arch_spawn_instance(struct kimage *image, struct mk_instance *instance, | ||
| int cpu) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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| int mk_arch_release_instance(struct mk_instance *instance) | ||
| { | ||
| return 0; | ||
| } | ||
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| int mk_arch_confirm_parked(struct mk_instance *instance, | ||
| mk_phys_cpu_t phys_cpu) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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| int mk_repark_instance_to_host(struct mk_instance *instance) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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| int mk_repark_cpu_to_instance(struct mk_instance *instance, | ||
| mk_phys_cpu_t phys_cpu) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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| int mk_repark_cpu_to_host(struct mk_instance *instance, | ||
| mk_phys_cpu_t phys_cpu) | ||
| { | ||
| return -EOPNOTSUPP; | ||
| } | ||
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mk_enter_pool_state()panics the host. If the generic core reaches this on a CPU-pool path (it is the__noreturnhook other arches use when offlining a CPU into the pool), an unsupported operation takes down the whole host instead of failing the offline request. Same intent-vs-behavior mismatch: better to reject the pool transition earlier (e.g. frommk_arch_register_cpu()or a capability check) so this hook is never reached.There was a problem hiding this comment.
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Fixed in dcc1932 with a temporary ARCH_HAS_MK_POOL_STATE capability. x86 enables it; the RISC-V skeleton leaves it disabled. mk_do_cpu_remove() checks the capability before marking or offlining the CPU and returns -EOPNOTSUPP, so generic pool and hotplug removal paths cannot reach mk_enter_pool_state() on RISC-V. The rv64 Image build and an x86 focused hotplug build both pass.