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Support RISC-V resource scopes and rebalance compiler CI - #36

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284km merged 1 commit into
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feat/riscv-with-and-ci-rebalance
Nov 7, 2026
Merged

284km merged 1 commit into
mainfrom
feat/riscv-with-and-ci-rebalance

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@284km 284km commented Nov 7, 2026 •

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RV32 and RV64 now execute scope-bound with-expressions. Lower them before reachability, closure capture and frame sizing into ordinary bindings and a close continuation. Acquire once, retain the body result across cleanup, preserve LIFO order and keep calls from bypassing cleanup through tail-call emission. Existing failure propagation remains: closes run after normal return, with no exception finalization. OwnedVec storage keeps the target's arena lifetime.

The complete factory fixture now executes on both RISC-V widths. Add a scope fixture covering generated-name collisions, captured closes, source shadowing, parameterized Drop records, sixteen nested resources that spill frame bindings, result values and caught/escaping failures. Hosted boundary checks require both fixtures to compile, exit successfully and match explicit output oracles at both widths; they cannot silently become allowed corpus refusals.

The scope fixture also fixes existing backend defects: Wasm loads close fields with the current eight-byte record layout, wraps pointers for memory accesses and supplies i64 closure arguments; LLVM extracts close from the instantiated record aggregate and uses the current i64 unit calling convention.

Move the README execution gate from compiler to containers. Retain its forced full-suite rerun, README transcript and newcomer-program check, along with the separate compiler unit-suite step. Pin the gate's name, command and destination in the routing validator and require dune in the containers preflight. Keep all 191 gates, nine groups, four build configurations and the existing required-check name.

Validation

  • Factory and scope fixtures match interpreter/C/LLVM/Wasm and execute on RV32/RV64 with explicit expected output.
  • The real RISC-V contract harness rejects injected compile refusals and exit 23 after otherwise matching output at both widths.
  • Partition audit retains 1,054 fixture compiler invocations across all-mode and its complementary partitions.
  • Routing controls cover 46 invalid configurations, 36 result combinations, eight checkout controls and 64 setup controls; eleven tool-preflight controls pass.
  • Final local checks pass: 2,946 unit tests, 251 parity fixtures in the inventory, ten README commands, workflow syntax and documentation coverage/claims.

Hosted PR CI passes all 17 jobs and all 191 gates, once each in their assigned group. Execution logs confirm the moved README gate, both unit-suite checks, all 251 parity programs, all 84 snapshot refusals, all three real RISC-V modes and the four required factory/scope oracle runs. RV32 has 222 agreements and seven expected differences; RV64 has 246 agreements and two expected differences.

Merged-main CI also passes all 17 jobs and all 191 gates on the merged source. All execution markers are verified again, and Pages builds and deploys that same commit. The merged tree matches the tested PR tree.

Run Compiler Containers Whole workflow
Preceding main 19m46s 16m49s 25m14s
PR #36 17m06s 17m33s 24m42s
Merged main 20m13s 15m06s 23m23s

These individual runs vary with setup, cache state and runner load. An overall reduction is observed in these runs, while a stable compiler-group speedup is not established. The gate transfer retains every verification. Focused paired local compilation of three unchanged inputs at RV32/RV64 has medians of 0.93–1.01 times the published v0.1.712 compiler; that sample does not establish hosted-job throughput.

These changes are unreleased. Published v0.1.712 was built and independently verified from its separate reviewed release source.

@284km
284km merged commit ee904d8 into main Nov 7, 2026
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@284km
284km deleted the feat/riscv-with-and-ci-rebalance branch November 7, 2026 10:24
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