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Add PPE42 (PowerPC Embedded) architecture support - #396
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Copilot review overview
7 open issues
rlwimirequires register operands for the first two… · Newrlwimirequires register operands for the first two… · New#elifcannot appear after an#endif. As written, this… · Newskip(usize_bytes - addr_size)using subtraction; ifaddr_sizeis… · Newskip(usize_bytes - addr_size)using subtraction; ifaddr_sizeis… · NewUSE_PHYSICAL_ADDRESSES: true(embedded/no-MMU), butsimplify()always performs… · New8011-8015map to1-5, but the code normalizes8010as well (mapping… · New
What changed in this PR
Adds PPE42 (PowerPC Embedded) architecture support, including Simics-side tracing/decoding and a C/C++ harness header for emitting PPE42-compatible magic instructions.
Changes:
- Introduce a new PPE42 architecture module with instruction classification and compare extraction.
- Extend architecture selection and start/write logic to support physical-address-only and big-endian targets.
- Add PPE42 harness headers and normalize SBE-range magic numbers to TSFFS standard magic numbers.
| File | Description |
|---|---|
| src/lib.rs | Normalizes SBE magic-number range to TSFFS standard magic numbers before dispatch. |
| src/arch/ppe42.rs | Adds PPE42 ArchitectureOperations + PPE42 instruction decoder/disassembler for tracing. |
| src/arch/mod.rs | Wires PPE42 into arch selection and adds physical-address + big-endian handling in shared routines. |
| harness/tsffs.h | Attempts to include a PPE42-specific harness header under PPC defines. |
| harness/tsffs-gcc-ppe42.h | Adds PPE42 magic-instruction macros and TSFFS harness macros for PowerPC/PPE42. |
Review effort: Lite
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| #define __ppe42_magic(n) \ | ||
| __asm__ __volatile__("rlwimi %0,%0,0,%1,%2" \ | ||
| : \ | ||
| : "i" (((n) >> 8) & 0x1f), \ | ||
| "i" (((n) >> 4) & 0xf), \ | ||
| "i" ((((n) >> 0) & 0xf) | 16) \ | ||
| : ) | ||
|
|
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| #define __ppe42_magic_extended1(n, arg0) \ | ||
| __asm__ __volatile__("mr 10, %0; rlwimi %1,%1,0,%2,%3" \ | ||
| : \ | ||
| : "r"(arg0), \ | ||
| "i" (((n) >> 8) & 0x1f), \ | ||
| "i" (((n) >> 4) & 0xf), \ | ||
| "i" ((((n) >> 0) & 0xf) | 16) \ | ||
| : "r10") |
Comment on lines
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| #endif // TSFFS_H | ||
| #elif defined(__PPC__) || defined(__ppc__) || defined(__powerpc__) || defined(_ARCH_PPC) | ||
| #include "tsffs-gcc-ppe42.h" | ||
| #else | ||
| #error "Unsupported platform!" | ||
| #endif |
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| let addr_size = if let Some(width) = Self::POINTER_WIDTH_OVERRIDE { | ||
| width as usize | ||
| } else { | ||
| self.processor_info_v2().get_logical_address_width()? as usize / u8::BITS as usize | ||
| }; |
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| let len_bytes = if Self::BYTE_ORDER_BIG_ENDIAN { | ||
| testcase | ||
| .len() | ||
| .to_be_bytes() | ||
| .iter() | ||
| .skip(usize::BITS as usize / u8::BITS as usize - addr_size) | ||
| .copied() | ||
| .collect::<Vec<u8>>() | ||
| } else { | ||
| testcase | ||
| .len() | ||
| .to_le_bytes() | ||
| .iter() | ||
| .take(addr_size) | ||
| .copied() | ||
| .collect::<Vec<u8>>() |
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| let address = self | ||
| .processor_info_v2 | ||
| .logical_to_physical(a, Access::Sim_Access_Read)?; | ||
| Ok(CmpValue::U64(read_phys_memory( | ||
| self.cpu, | ||
| address.address, | ||
| size_of::<u64>() as i32, | ||
| )?)) | ||
| } | ||
| CmpValue::U32(a) => { | ||
| let address = self | ||
| .processor_info_v2 | ||
| .logical_to_physical(a as u64, Access::Sim_Access_Read)?; | ||
| Ok(CmpValue::U32(read_phys_memory( | ||
| self.cpu, | ||
| address.address, |
Comment on lines
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| // Normalize SBE magic numbers (8010-8015 range) to standard range (1-5) | ||
| // SBE uses magic numbers in range 8000-8190, TSFFS uses 8010-8015 | ||
| // 8011-8015 map to 1-5 (start/stop) | ||
| let normalized_magic = if magic_number >= 8010 && magic_number <= 8015 { | ||
| magic_number - 8010 | ||
| } else { | ||
| magic_number | ||
| }; |
Contributor
|
Hi @Manideep-Bhupalam Can you add at least a minimal description ? Launched CI + Copilot, please take care of any failing test / copilot review. Thanks |
Copilot stopped reviewing on behalf of
Wenzel due to an error
October 28, 2026 11:31
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