Math + CE @ Northwestern |
Prev @ Hidden Road / Ripple Prime
- NYC & Chicago
-
10:34
(UTC -04:00) - https://aaryapatel.vercel.app/
- in/aarya-p9
Pinned Loading
-
-
verified-RTL-synthesis-pipeline
verified-RTL-synthesis-pipeline PublicAgent-driven stepwise refinement and formal verification of RTL from natural language
Python 3
-
Teeny-Tiny
Teeny-Tiny Public templateForked from TinyTapeout/ttihp-verilog-template
Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects
Verilog
-
esp32-audio-classifier
esp32-audio-classifier PublicReal-time music genre classification on ESP32 using DSP feature extraction and TensorFlow Lite for EdgeML capabilities
C++
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.
