GPU / AI Systems · Systems Performance · Embedded / FPGA / SoC
M.S.E. Electrical Engineering @ University of Pennsylvania (2026–2028)
Building hardware-aware software from real measurements: multi-GPU inference, reliable serving, performance-oriented C++, and register-level systems.
Python · Go · C/C++ · CUDA C++ (Tensor Cores) · CUDA/NCCL · ARM NEON · Vitis HLS · Linux
Open to Summer 2027 internships in GPU/AI systems, embedded software, and hardware-aware performance engineering.
yuchenhe985.github.io · LinkedIn · yuchenhe.work@outlook.com
| Project | Engineering focus | Evidence |
|---|---|---|
| RadixGates | Failure-tolerant Go gateway for multi-GPU LLM serving: prefix affinity, health-aware failover, circuit breaking, admission control, and OpenAI-compatible routing | Node-crash clean completions 85.2% → 99.7% under identical injected faults (simulated workers); on three real llama.cpp workers, found spill-on-full routing cut prefix-cache hits 59.1% → 24.4%; 55 tests under go test -race |
| lowbit-kernels | INT4 weight-only CUDA kernels (GEMV ladder to mma.sync tensor cores) as a drop-in layer for Qwen2.5, with dispatch chosen from a measured batch sweep | At batch 1, 0.34–0.69× the FP16 weight-streaming time (deployed variant 0.43–0.74×); CUDA-graph decode 1.37–2.01× FP16; 3B memory 7.85 → 3.64 GB; decode kernels match a fake-quant reference on 99.2–100% of next tokens |
| llm-serving-eval-kit | GPU-memory sizing, topology interpretation, startup-log diagnosis, repeated benchmark matrices, and confounder-aware comparison | 11 failure signatures, bootstrap intervals, cost/SLO reporting, and 39 unit/end-to-end tests |
| cdc-chunker | C++17 Gear/Rabin content-defined chunking with streaming and bit-identical parallel output | About 2.0 GB/s sequential and 7.4 GB/s with 8 threads on Apple M1; 31 tests plus 23/23 mutation checks |
| llm-finetune-lab | Local text-to-SQL feasibility study: LoRA/DDP, execution-based evaluation, GGUF deployment, and guardrail analysis | 398 MB Q4 model, 82.6% execution accuracy, 1.76× two-GPU training speedup; evidence-based human-in-the-loop release decision |
Measured on the target hardware. The code is not public; method and results are below.
| Project | Engineering focus | Evidence |
|---|---|---|
| FPGA matrix-multiply accelerator (Vitis HLS, Ultra96 / Zynq UltraScale+) | Traced an II=4 stall to memory read ports and fixed it by complete array partitioning; C/RTL co-simulation; on-board timing and an offload cost model | II=4 → II=1 at 150 MHz, 320/360 DSPs; 1.15× vs -O3 Cortex-A53 per kernel; break-even at N ≈ 395 once OpenCL setup is counted |
| Cortex-A53 pipeline + NEON (Ultra96) | Profiled on the target, split a four-stage video pipeline across two cores at a measured point, hand-wrote NEON intrinsics | 53.2 → 97.4 frames/s (1.83×), bit-exact; NEON kernel 1.34× over -O3 scalar |
| 6T SRAM bitcell + 4-bit MAC macro (18 nm FinFET, Cadence) | β sweep to pick fin counts, DRC/LVS-clean custom layout, post-layout extraction; 16×4 array with decoder, sense amps and MAC under FSM control | Extracted read/hold SNM 150/270 mV at 0.8 V, still 96 mV read SNM at 0.5 V; hand model within 18 mV of simulation |
| AVR input-capture firmware (ATmega328PB) | Timer1 input-capture ISR with a 32-bit software overflow count and atomic snapshots; race handling proved on a host build | 0 mismatches in 100 million random captures; without the wrap rule about 8% were off by a period |
| Project | Engineering focus | Evidence |
|---|---|---|
| conference-ops | Spring Boot 3 + PostgreSQL 16 backend: row-locked seat allocation with a FIFO waitlist, exclusion constraints against double-booking, idempotent retries, optimistic locking, Flyway | 60 concurrent requests for 10 seats never oversell (the test fails when the lock is removed); 25 integration tests on real PostgreSQL |
| review-pipeline | Python/DuckDB/Parquet pipeline: data contracts with quarantine, content-addressed idempotent stages, point-in-time features, leakage-safe evaluation | 494K real reviews in about 45 s; a random split would overstate R² 4.6×; top-decile helpful rate 2.13× the base rate |
| budget-manager | Java 17/JavaFX desktop app on SQLite: integer-cent money, versioned migrations, all-or-nothing CSV import, verified backup and restore | 40 JUnit tests; schema upgrades keep existing data; a damaged backup is refused with live data untouched |
Four short notes on what a measurement taught me, on my site:
- A simulation can't see a cache: my gateway's failure tests all passed, and a routing rule I had added still cut prefix-cache hits from 59.1% to 24.4% on real engines.
- The wrong answers that raise no error: the 16.4% of a fine-tuned model's SQL that runs cleanly and returns the wrong rows.
- Same weights, different dtype: only 27.6% of a fine-tuned model's bytes match its base, and the encoding mattered more than the chunker.
- Average chunk size isn't what an edit costs: an edit is more likely to land in a big chunk, so the spread of chunk sizes matters as much as the average.
- Measure before optimizing: record topology, software versions, failure modes, repetitions, and uncertainty before attributing a result.
- Design for failure: make overload, node loss, partial streams, and invalid model output explicit instead of hiding them behind averages.
- Follow the hardware: connect routing, cache locality, communication topology, memory limits, and parallelism choices to observed behavior.
Moving down the stack from serving systems toward accelerators: low-bit GPU kernels, FPGA offload, register-level firmware and custom memory circuits, each judged by what it measures on real hardware. Earlier, at Shopee, I built PySpark/Hive pipelines and data-quality checks for a regional logistics forecasting platform.