Reviving, preserving, and documenting Intel Xeon Phi Knights Corner (KNC) coprocessors and the K1OM architecture through open-source engineering, reproducible research, and practical software-development tooling.

The Xeon Phi Revival Project is an AI-assisted, Codex-driven preservation, research, and engineering effort focused on restoring useful development paths for Intel Xeon Phi Knights Corner hardware. The project combines XPR-OS, K1OM/Linux userspace work, compiler and ABI research, software ports, hardware bring-up, Intel MPSS interoperability, recovery tooling, and preservation of historical Xeon Phi technical knowledge.

The goal is broader than producing an operating system: we want these unusual manycore coprocessors to remain understandable, bootable, programmable, and useful to hobbyists, researchers, developers, and hardware-preservation communities long after their original software ecosystem disappeared.

Hello, I am @CarlsonDataCenter, and I am the maintainer and overarching manager of this project. I am a high schooler who thought that this would be a fun learning project to try and build back up an old, obscure piece of technology, the Intel Xeon Phi Coprocessor. With the mainstream of AI, I'm able to use Codex to make this project possible, as I know 0 zero code but have a background in hardware, servers, basic shell, etc. This project goes to show how helpful AI can be used, when used rightly. The majority of the code and descriptions are AI-generated, but they are audited by me, and changes I direct are implemented. So, I continue with the project.

XPR-OS is the project's revived Linux operating environment for Intel Xeon Phi Knights Corner / K1OM. The current public milestone, XPR-OS 0.1.0-rc7, uses a project-built K1OM-compatible kernel, rebuilt MIC modules, a public and source-accounted userspace/runtime, micveth networking, Dropbear SSH, and a project-controlled bootstrap-to-final-root boot path. RC7 includes packaged xpr-init and source-accounted CPython 3.12.13 core, with corresponding source, SPDX, notices and checksums. Independent G2 staging reproduced both archives byte-for-byte.

RC7 is a prerelease and has been hardware-tested on an Intel Xeon Phi 5110P. Other Knights Corner cards are not yet project-validated, and Knights Landing (KNL) is a different platform and is not an XPR-OS target.

xpr-init is the validated host-side installation, integration, and recovery helper for XPR-OS on the tested Intel MPSS setup. It simplifies the previously manual deployment process while keeping Intel micctrl responsible for normal Xeon Phi hardware control.

On the tested CentOS 7.4 + MPSS 3.4.10 + Xeon Phi 5110P configuration, the validated user flow is:

xpr-init --install
        ↓
micctrl reset / wait / boot
        ↓
automatic bootstrap and final-root handoff
        ↓
ssh xpr-mic0
        ↓
xpr-init --recover
        ↓
stock MPSS restored; ssh mic0

The live validation reached final XPR /sbin/init as PID 1, micveth networking, authenticated final-root SSH, and native hello, pthread, and dlopen smoke programs and Python core/threading operations before restoring the exact stock MPSS configuration. XPR uses a separate persistent server identity and strict host-key checking; normal stock SSH trust remains isolated.

The standalone source-built K1OM toolkit is technically validated, but its publication remains held for qualified review of separate KNC-binutils terms. It is not bundled with RC7. Historical/toolchain research continues separately.

The project currently makes a strong hardware claim only for the Intel Xeon Phi 5110P (Knights Corner). The tested host configuration is CentOS 7.4 with Intel MPSS 3.4.10, already installed and working. Fresh host-OS/MPSS installation from scratch was not validated. MPSS remains separately obtained and required for the tested host-control path. RC7 is experimental, not a modern production Linux distribution. Python optional extensions are not fully covered; the known <exec_prefix> warning may appear despite passing core tests.

The project deliberately distinguishes:

• hardware-validated results from assumptions;
• Knights Corner (KNC/K1OM) from Knights Landing (KNL);
• current supported procedures from preserved historical research; and
• project/open-source material from Intel software that must be obtained separately under its applicable terms.

If you want to run XPR-OS:

1. Read the Getting Started guide.
2. Check supported hardware.
3. Install or verify MPSS 3.4.10.
4. Download XPR-OS RC7.
5. Install and use the packaged xpr-init.

If you want to study or contribute:

• Main project repository
• Project documentation
• Concepts and architecture
• Development documentation
• Historical and reverse-engineering research
• Contributing

The longer manual RC6 installation procedure is retained for advanced users, troubleshooting, and understanding the underlying boot process, but xpr-init is the recommended beginner path for the tested configuration.

The main engineering and research repository. It contains XPR-OS source and release material, xpr-init, K1OM tooling research, tests, documentation, release evidence, historical technical records, and software-port work.

This is explicitly an AI-assisted and Codex-driven project. Codex and other AI tools are used heavily for implementation, code generation, analysis, documentation, auditing, and translating historical technical evidence into repeatable experiments.

AI output is not treated as hardware evidence by itself. Project claims are accepted only when they are supported by source review, reproducible build or test evidence, and—where hardware behavior is involved—results captured from real Xeon Phi systems.

That distinction is central to the project: AI accelerates the engineering, while physical testing and reproducible evidence determine what the project can actually claim.

Evidence before assumptions.
Rollback before risky hardware changes.
Open project work separated from proprietary Intel components.
Historical research preserved, but never confused with current instructions.

The project emphasizes source provenance, reproducibility, rollback safety, clear documentation, and preserving the reasoning and evidence behind the revival—not merely producing binaries that happen to boot.

This project may be useful to people researching Intel Xeon Phi, Xeon Phi 5110P, Knights Corner, KNC, K1OM, Intel MIC, Many Integrated Core, Intel MPSS, Xeon Phi Linux, Xeon Phi uOS, K1OM compiler, K1OM toolchain, or efforts to boot, program, preserve, or revive Intel Xeon Phi coprocessors.

Intel, Xeon, and Xeon Phi are trademarks of Intel Corporation. The Xeon Phi Revival Project is independent and is not affiliated with, sponsored by, endorsed by, or supported by Intel.

Intel MPSS host software, firmware, historical Intel userspace, compiler installers, and other proprietary or separately licensed Intel components are not redistributed by the project unless redistribution rights are clearly established. Project-authored material is generally MIT-licensed, while third-party material retains its original licenses and notices.