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SharmaSaurabh-git/README.md 
┌─────────────────────────────────────────────────────────┐
│  x(t) ──▶ [ECE Undergrad] ──▶ [DSP] ──▶ [VLSI] ──▶ y(t)  │
│                    HPTU · Class of 2028                   │
└─────────────────────────────────────────────────────────┘

> about

I'm an Electronics & Communication Engineering student building toward Verification Engineering in the VLSI industry. My path runs through signal processing first — filters, spectral analysis, modulation — because that's where the intuition for "what a signal actually looks like" comes from before you're staring at RTL and waveforms all day.

I build things that run, not things that just look like they run. Every repo below has a real test suite and I can walk through any line of it.


> currently

+ Building out a Verilog/SystemVerilog foundation
+ Maintaining 3 verified hardware/DSP repos, test suites passing on all
+ Following an 18-month roadmap toward VLSI verification internships

> projects

🔲 ai-hardware-accelerator

An output-stationary systolic array for matrix multiplication in SystemVerilog — the core computational pattern behind TPU/Tensor-Core style AI accelerators.

What's in it:

  • Parameterizable N×N array, each PE owns and accumulates one output element independently
  • Correctly time-skewed input feed (documented cycle-by-cycle derivation)
  • Verified: 32/32 output elements correct across 2 test cases, run in Icarus Verilog — see doc/architecture.md for the full design writeup, including why an earlier version was architecturally wrong and how it was fixed

SystemVerilog Icarus Verilog Digital Design

🧮 picosrv32

A 5-stage pipelined RISC-V CPU core (RV32I subset) — real forwarding, a load-use stall, and branches that resolve and flush correctly.

What's in it:

  • Full EX/MEM + MEM/WB forwarding, same-cycle register-file bypass
  • R-type/I-type ALU ops, loads, stores, BEQ/BNE branches
  • Verified: 14/14 checks correct on a 16-instruction test program covering every hazard type it handles, run in Icarus Verilog — see doc/architecture.md for why the earlier version never even compiled

SystemVerilog Icarus Verilog Computer Architecture

📡 signal-processing-toolkit

A Python DSP library built from the ground up — not a wrapper, an actual toolkit with validated math.

What's in it:

  • FIR filter design (low-pass/high-pass/band-pass/band-stop) + both causal and zero-phase filtering
  • Spectral analysis: FFT, Welch PSD, spectrogram, STFT
  • AM/FM analog modulation, BPSK/QPSK digital modulation
  • 46-test suite, CI on every push

Python NumPy SciPy Matplotlib pytest

📶 2.4 GHz Microstrip Patch Antenna

Designed and simulated a patch antenna for the 2.4 GHz ISM band as a team B.Tech project — full workflow from geometry design through S-parameter validation.

What it involved:

  • RF simulation and structure design in Ansys HFSS
  • Return loss / bandwidth / radiation pattern analysis
  • Team project — built and validated with 3 collaborators

Ansys HFSS RF Design Antenna Theory

> toolchain

Languages

Python    ████████░░  
MATLAB    ██████░░░░  
C         █████░░░░░  
Verilog   ███░░░░░░░  learning

Tools

Git & GitHub
Scilab
Ansys HFSS
Linux / Termux

Focus areas

Digital Signal
  Processing
RF / Antenna
  Design
VLSI
  Verification

> metrics




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