Design Verification / Pre-Silicon Verification | SystemVerilog · UVM · SVA · Python
2025 ECE graduate building digital hardware and self-checking verification environments. My work focuses on protocol checking, reference-model scoreboards, CPU RTL debug, scoped coverage and reproducible regressions.
Based in Rajahmundry, India · Bengaluru preferred · open to relocation
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| Project | Engineering work | Evidence |
|---|---|---|
| AXI4-Lite UVM verification | UVM agent, scoreboard, RAL, covergroups, SVA, independent protocol oracle and actual-DUT bounded safety checks | Verilator/UVM regression: 344 writes, 108 reads, zero data/response mismatches or UVM errors/fatals. Separate 1,075-pair oracle detects two RTL mutants; bounded safety through 24 steps on a four-word instance. |
| Five-stage RISC-V CPU | RV32I-subset RTL, forwarding, load-use stalls, branch/JAL flushes and retirement tracking | 44 Python-oracle programs plus retirement/decode checks; delayed-writeback dependency and retirement-accounting defects found and fixed. |
| Memory-controller verification | Modular SystemVerilog testbench and independent cycle oracle for a 256×32 request/response memory | 2,200 traffic cycles and 1,329 read responses checked, including pipelined reads, mixed traffic and reset cancellation. |
| Signed matrix MAC verification | Independent Python model for signed arithmetic, saturation, streaming latency and reset | 2,022 matrix comparisons across six configurations; all 11 defined manual coverage bins hit. |
Each repository documents its tests, commands, results and limitations. The CPU implements a subset of RV32I; the memory project is not a DDR4 controller; the MAC is a matrix compute block rather than a complete AI accelerator. Coverage results apply to the explicitly defined bins and runs.
These are separate protocol and tooling exercises, rather than additional flagship projects.
| Area | Repository | Distinct purpose |
|---|---|---|
| Protocol translation | AXI4-Lite packet bridge | Independent AW/W capture, packet backpressure and completion/error routing; 1,075 oracle write/read pairs. Educational packet format, not PCIe-compliant hardware. |
| Serial protocol DV | SPI master with cocotb | Slave BFM and bidirectional scoreboard across four CPOL/CPHA modes. |
| Register-interface DV | APB register file with cocotb | SETUP/ACCESS sequencing, reference-model checking and error paths. |
| Synthesis verification | RTL synthesis and equivalence | 32-bit combinational ALU; 8,200 oracle vectors against RTL and a fresh generic netlist; 32 output-bit equivalence cells proven. No completed physical-design flow. |
- Scan-chain and stuck-at ATPG: small educational DFT exercise.
- Registered-ALU synthesis / timing lab: separate 8-bit registered ALU, synthesis reports and an OpenSTA script; logic-depth estimates are not measured timing signoff.
- Earlier standalone AXI assertion demo: historical example. The main AXI repository above is the maintained portfolio reference.
- Verification: SystemVerilog, UVM/RAL, scoreboards, constrained stimulus, SVA, functional coverage and protocol debug.
- RTL: Verilog/SystemVerilog, FSMs, pipelines, hazards/forwarding and AXI4-Lite interfaces.
- Automation: Python, cocotb, Make, GitHub Actions, Git and Linux.
- Executed main-project flows: Icarus Verilog, Verilator/UVM and Yosys simulation/formal/synthesis workflows.
Seeking entry-level Design Verification / Pre-Silicon Verification, followed by RTL / Digital Design and hardware-focused Validation / Emulation opportunities.