UART (Universal Asynchronous Receiver Transmitter) | Verilog HDL

A synthesizable Verilog HDL implementation of a Universal Asynchronous Receiver Transmitter (UART) featuring independent Transmitter (TX) and Receiver (RX) modules. The design enables asynchronous serial communication and includes functional verification through simulation.

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Overview

UART is one of the most widely used serial communication protocols in embedded systems, microcontrollers, FPGAs, and ASIC designs. This project demonstrates the RTL implementation of UART communication using Verilog HDL with complete transmission and reception functionality.

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Features

• UART Transmitter (TX)
• UART Receiver (RX)
• Asynchronous Serial Communication
• Start and Stop Bit Detection
• Configurable Baud Rate
• Synthesizable RTL Design
• Functional Testbench
• Xilinx Vivado Compatible

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UART Frame Format

Field	Bits
Start Bit	1
Data Bits	8
Stop Bit	1

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Project Structure

UART_Verilog
│
├── rtl/
│   ├── uart_tx.v
│   ├── uart_rx.v
│   ├── baud_generator.v
│   └── uart_top.v
│
├── tb/
│   └── uart_top_tb.v
│
├── images/
│   ├── rtl_schematic.png
│   └── waveform.png
│
└── README.md

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RTL Schematic

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Simulation Waveform

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Applications

• Serial Communication
• FPGA and ASIC Designs
• Embedded Systems
• Microcontroller Interfaces
• Sensor Communication
• Debug Consoles

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Tech Stack

• Verilog HDL
• Xilinx Vivado
• Digital Electronics
• RTL Design
• Git & GitHub