[Extraction][ext2spice]: Coupling caps are connected to "device terminal" of resistors, giving floating capacitors

[tskaar]

Hi!

When extracting some metal lines, I noticed that some of the capacitors extracted were not connected to anything (NGSpice/Xyce reported them as floating nets). Looking at the EXT file, I noticed that it referencing the device terminal (not sure whether this is the correct terminology...), e.g.:

device devres None -36 -7 -35 -6 0.11 "m1_n36_n7#" 0 0 "RL.A" 100 205000,4300 "RL.B" 100 205100,4302
                                      ^^^^^^^^^^^

Where this terminal is not output, unless ext2spice resistor tee on is set. In the case it's not set, I would expect the capacitor to be split between the other two terminals (RL.A, RL.B) in the case above.

Test case

GDS is three metal1 lines:

Where each line is split using a metal resistor, the three different lines are annotated as RL (left), RC (center) and RR (right), and each top port is then RX.A and bottom port is RX.B

Extracting this using:

# Generated by kpex 0.4.1
crashbackups stop
drc off
gds read resistor_coupling.gds
load TOP
select top cell
flatten TOP_flat
load TOP_flat
cellname delete TOP -noprompt
cellname rename TOP_flat TOP
select top cell
extresist threshold 0
extresist minres 0
extresist mindelay 0
extract path output
extract no capacitance
extract do coupling
extract no resistance
extract all
ext2spice short none
ext2spice merge none
ext2spice cthresh 0.0
ext2spice subcircuits top on
ext2spice format ngspice
ext2spice resistor tee off
ext2spice -p output -o output/TOP_resistor_tee_off.spice
quit -noprompt

i.e. we only want to extract coupling (no resistors, nor caps to substrate).

This gives TOP.ext:

timestamp 0
version 8.3
tech ihp-sg13g2
style ngspice()
scale 1000 1 0.5
resistclasses 3000000 67000 110 88 88 88 88 18 11 7000 260000 1360000
port "RR.B" 7 236 -2057 336 -1957 m1
port "RR.A" 4 236 2042 336 2143 m1
port "RC.B" 6 100 -2057 200 -1957 m1
port "RC.A" 3 100 2042 200 2143 m1
port "RL.B" 5 -36 -2057 64 -1957 m1
port "RL.A" 2 -36 2042 64 2143 m1
node "RR.B" 2 0 236 -2057 m1 0 0 0 0 205100 4202 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "m1_236_n7#" 0 0 236 -7 rm1 0 0 0 0 10000 200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "RR.A" 2 0 236 2042 m1 0 0 0 0 205000 4200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "RC.B" 2 0 100 -2057 m1 0 0 0 0 205100 4202 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "m1_100_n7#" 0 0 100 -7 rm1 0 0 0 0 10000 200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "RC.A" 2 0 100 2042 m1 0 0 0 0 205000 4200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "RL.B" 2 0 -36 -2057 m1 0 0 0 0 205100 4202 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "m1_n36_n7#" 0 0 -36 -7 rm1 0 0 0 0 10000 200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "RL.A" 2 0 -36 2042 m1 0 0 0 0 205000 4200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "sub!" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "RC.A" "RL.A" 1132.82
cap "RR.A" "RC.A" 1132.82
cap "m1_236_n7#" "m1_100_n7#" 55.2596
cap "RC.B" "RR.B" 1133.37
cap "m1_100_n7#" "m1_n36_n7#" 55.2596
cap "RC.B" "RL.B" 1133.37
device devres None 236 -7 237 -6 0.11 "m1_236_n7#" 0 0 "RR.A" 100 205000,4300 "RR.B" 100 205100,4302
device devres None 100 -7 101 -6 0.11 "m1_100_n7#" 0 0 "RC.A" 100 205000,4300 "RC.B" 100 205100,4302
device devres None -36 -7 -35 -6 0.11 "m1_n36_n7#" 0 0 "RL.A" 100 205000,4300 "RL.B" 100 205100,4302

And from this we get the SPICE netlist TOP_resistor_tee_off.spice:

* NGSPICE file created from TOP.ext - technology: ihp-sg13g2

.subckt TOP RL.A RC.A RR.A RL.B RC.B RR.B
R0 RC.A RC.B 0.110000
R1 RR.A RR.B 0.110000
R2 RL.A RL.B 0.110000
C0 RC.B RL.B 1.13337f
C1 RC.A RL.A 1.13282f
C2 m1_n36_n7# m1_100_n7# 0.05526f
C3 RR.B RC.B 1.13337f
C4 m1_100_n7# m1_236_n7# 0.05526f
C5 RR.A RC.A 1.13282f
.ends

Where C2,C4 are the problematic (floating) capacitors:

C2 m1_n36_n7# m1_100_n7# 0.05526f
C4 m1_100_n7# m1_236_n7# 0.05526f

Where m1_n36_n7# is the "device terminal" for RL line, m1_100_n7# is the terminal for RC and m1_236_n7# is the terminal for RR.

Workaround

If I enable ext2spice resistor tee on, I instead get the netlist:

.subckt TOP RL.A RC.A RR.A RL.B RC.B RR.B
R0A m1_100_n7# RC.A 0.055000
R0B m1_100_n7# RC.B 0.055000
R1A m1_236_n7# RR.A 0.055000
R1B m1_236_n7# RR.B 0.055000
R2A m1_n36_n7# RL.A 0.055000
R2B m1_n36_n7# RL.B 0.055000
C0 RC.B RL.B 1.13337f
C1 RC.A RL.A 1.13282f
C2 m1_n36_n7# m1_100_n7# 0.05526f
C3 RR.B RC.B 1.13337f
C4 m1_100_n7# m1_236_n7# 0.05526f
C5 RR.A RC.A 1.13282f
.ends

Which has the required ports/terminals

Expectations(?)

Would it make sense that when ext2spice resistor tee off is set that we split the capacitor across the two (other) terminals of the resistor, i.e. in this case one would add:

C0 RC.B RL.B 1.13337f
C1 RC.A RL.A 1.13282f
* C2 m1_n36_n7# m1_100_n7# 0.05526f ; Original capacitor
C2a RC.A RL.A 0.02763f  ; C2/2
C2b RC.B RL.B 0.02763f  ; C2/2

Where C0 and C2a, C1 and C2b could also be merged to simplify the netlist.

Software used

Magic: v8.3.683
PDK: ihp-sg13g2, dev branch, commit@2bbec755dc67ca3db0261c3d6163e15735d66710
OS: ArchLinux x86_64

Attachment

testcase_resistor_coupling.tar.gz

This has:

resistor_coupling/
    resistor_coupling.gds - GDS file with the three metal lines
    extract_resistor_tee_off.tcl - TCL script to extract netlist with ext2spice resistor tee off
    extract_resistor_tee_on.tcl - TCL script to extract netlist with ext2spice resistor tee on
    output/
        TOP.ext - Output from extract
         TOP_resistor_tee_off.spice - Spice netlist from extract_resistor_tee_off.tcl
         TOP_resistor_tee_on.spice - Spice netlist from extract_resistor_tee_on.tcl

Let me know if you need anything from me, thanks!