fpga_diff: add UVHS XiangShan and GBus support - #163
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Preserve shared DiffTest AXIS framing and workload DDR H2C. Add GBS1 register and GBD1 local SRAM DMA endpoints with backpressure, remove obsolete DDR C2H trace/ring paths, and add transport and supervisor regressions.
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Route GBus workload writes through the existing CPU-subsystem DMA AXI interface instead of a dedicated physical-DDR master. NutShell inserts a generated 256-to-64 AXI converter after the host-to-CPU CDC; KMH keeps the native 256-bit path and fails the file list when dma_* is missing. XDMA retains data_bridge, and GBus no longer exports or imports it. Remove the unused AXI3 arbiter, remote-link, and 64-to-256 converter left over from the rejected topology. The common UVHS DDR block is unchanged.
UVHS P4 still aborts infer_clock/transform_clock on protected GENERALBD sysbus LAST_VALUE pins even after exact config_clock -ignore. Keep the TCK diagnostics in the log and continue partition/PnR for GBus only.
U_UVHS_FLASH_GBUS is the UVHS ROM/flash path, not the DiffTest host interface. Gating it with CONFIG_DIFFTEST_HOSTIF_GBUS dropped the F0 clk6_n pair and failed bitstream DRC on IOSTDTYPE-1.
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This PR adds optional GBus transport support to the existing FPGA-Diff flow while preserving XDMA as the default interface.
The UVHS XiangShan GBus configuration has been validated on hardware with FPGA-Diff reaching HIT GOOD TRAP.