module mainaksil (
input wire clk,
input wire rst_n,
output reg [2:0] focus, // 000: ASIC | 001: FPGA | 010: RTL | 011: GDSII
output reg curiosity // never gated
);
// Hands-on across the full RTL-to-GDSII flow
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
focus <= 3'b010;
curiosity <= 1'b1;
end else begin
curiosity <= 1'b1; // always high, never resets
end
end
endmodule# report_status.tcl
read_design -source rtl/
set_top current_focus
foreach block { bitnet_bitlinear_accel des_asap7_pnr } {
puts "-- exploring: $block"
}
# STATUS
# [x] RTL-to-GDSII flow for a RTL on ASAP7 7nm (Genus -> Innovus -> PrimeTime)
# [~] BitNet b1.58 BitLinear kernel in Verilog, targeting a Zybo Z7-10 (Zynq-7000)
report_qor -summary| Layer | Tools |
|---|---|
| HDL | Verilog, SystemVerilog |
| Synthesis / PnR / Signoff | Cadence Genus, Cadence Innovus, Synopsys PrimeTime |
| Simulation | Xilinx Vivado |
| Scripting | TCL, Python |
| Languages | Python, C/C++, Embedded C, Assembly (8085, ARM) |
| Other | COMSOL Multiphysics (Semiconductor Module) |
