We aim to develop a synthesizable high performance open source RISC-V core. We have currently implemented an out of order unprivileged RV32I core with peripherals for interacting with UART and emitting VGA.
- Designing a CPU from Scratch - March 9, 2026
- Reaching Towards Out Of Order in Our CPU - June 14, 2026
- Running DOOM on our Custom CPU and Going Viral - July 20, 2026
- Out of Order, on Technicality - RISCV - July 26, 2026
You'll need xpack-riscv-none-elf-gcc-15.2.0-1 install locally in this git repository so that scripts can access it at the path ./xpack-riscv-none-elf-gcc-15.2.0-1/...
The Nix flake is WIP and only supplies scala and verilator which is enough to build and run the core and simulation scripts manually.
Once your have your environment set up, you'll want to run ./scripts/generate-verilog.sh to generate verilog for verilator to run. Then run ./scripts/simulate.sh and pass in the path to the c program you wish to simulate. For example, ./scripts/simulate.sh ./programs/pong.c ./generated/pong.bin.
The simulation will emit frame.png under the ./generated/ folder. The image is a recording of the VGA signal and an approximation of what you might see when connected to a real VGA cable. It won't be completely accurate because the VGA clock is triggered at the same speed as the processor clock in simulation, which may not be the case in reality.
If you'd link to contribute, join the MIT OpenCompute discord and reach out to us there!
Made with love from Liam Hanrahan, Armaan Gomes, and contributors!