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WRISC-V

Goal

a functioning RV32G (unprivileged) implementation -- RISC-V Instruction Set Manual

Status

Extension Impl Test
I v v
M v v
A X X
F X X
D X X
Zicsr X X
Zifencei v X
C X X

Testing

Test suite: https://github.com/riscv-software-src/riscv-tests

cd riscv-tests/

riscv64-unknown-elf-gcc -march=<arch> -mabi=ilp32 -static -mcmodel=medany \
-fvisibility=hidden -nostdlib -nostartfiles \
-I./env/p -I./isa/macros/scalar \
-T./env/p/link.ld ./isa/<isa>/<file>.S \
-o <file>.elf

riscv64-unknown-elf-objcopy -O binary <file>.elf <file>.bin
cd riscv-tests/

riscv64-unknown-elf-objdump -d elf/<file>.elf

About

RISC-V CPU emulator (the 'W' is silent)

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