[AmnaxEhtsham]

Summary

This PR adds FreeRTOS+FAT support for Altera Agilex 5 SoC FPGA platforms.

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Changes

• Add the portable/SOCFPGA port.
• Add SDMMC block read/write support.
• Add USB Mass Storage Class block read/write support.
• Route block operations to SDMMC or USB based on the disk device address.
• Add CMake integration for the SOCFPGA port.
• Add faster free-cluster counting using multi-sector FAT reads.
• Add FAT32 FSInfo update support.
• Extend the disk structure to store the device address.
• Update relevant FreeRTOS+FAT configuration and public interfaces.

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Device selection

• Device address -1 selects SDMMC.
• Device addresses 0 and above select USB MSC.

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Original commits

• 41d64e2 Add support for Altera Agilex5 SoC FPGA
• d0a9230 Add portable layer for Agilex 5
• e7af08d Update SOCFPGA directory name
• 4910613 Fix SOCFPGA file headers
• 38f6478 Include msc_app.c in the FATFS CMake target

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Testing

• Tested on Agilex 5 (A5ED065BB32AE4S) with a Kingston DataTraveler 3.0 (57 GB) on USB3.

[htibosch]

Congratulations! And thank you for your big contribution.

I have reviewed it roughly. All part specific code and header files go into directory:

/portable/SOCFPGA

I have also looked at a USB interface. You let it depend on the block address, good idea.

Earlier, I have worked on this project:

\FreeRTOS-Plus-FAT\portable\Cyclone_V_Soc\alt_sdmmc.c
\FreeRTOS-Plus-FAT\portable\Cyclone_V_Soc\alt_sdmmc.h
\FreeRTOS-Plus-FAT\portable\Cyclone_V_Soc\ff_sddisk.c
\FreeRTOS-Plus-FAT\portable\Cyclone_V_Soc\main_fstest.c

but it never got on the rails.

[htibosch]

Haha, my initials: HT
I used to enable a WDT.

[htibosch]

Turning a number into a macro, very good!