ECAP5

Educational Computer Architecture Platform

⚙️ System-On-Chip implementation integrating ECAP5-DPROC

⚙️ RISC-V softcore for ECAP5

⚙️ Timer peripheral accessible through a Wishbone bus

⚙️ SPI peripheral implementation accessible through a Wishbone bus

⚙️ BRAM memory accessible through a Wishbone bus

⚙️ UART peripheral implementation accessible through a Wishbone bus

⚙️ Wishbone memory-mapped single-cycle interface

🧪 HDL testing libraries for ECAP5