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@Circuits-and-Systems-Lab-CASlab

Circuits and Systems Lab (CASlab)

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  1. UPSET UPSET Public

    UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

    Verilog 9 1

  2. LibreEDA LibreEDA Public

    A static timing analysis (STA) engine for open-source EDA flows.

    Verilog 2

  3. uth-pexconv uth-pexconv Public

    Parasitic extraction format converters for FasterCap and other field solvers

    Python 1

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Showing 3 of 3 repositories
  • LibreEDA Public

    A static timing analysis (STA) engine for open-source EDA flows.

    Circuits-and-Systems-Lab-CASlab/LibreEDA's past year of commit activity
    Verilog 2 BSD-3-Clause 0 0 0 Updated Sep 29, 2026
  • uth-pexconv Public

    Parasitic extraction format converters for FasterCap and other field solvers

    Circuits-and-Systems-Lab-CASlab/uth-pexconv's past year of commit activity
    Python 1 GPL-3.0 0 1 0 Updated Aug 27, 2026
  • UPSET Public

    UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

    Circuits-and-Systems-Lab-CASlab/UPSET's past year of commit activity
    Verilog 9 MIT 1 0 1 Updated Feb 19, 2026

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