Finding
During LR2021 throughput characterization for the variant PR (#2739), we measured RadioLib's per-packet RX pipeline overhead on ESP32-C3:
| Configuration |
Time/packet |
Throughput |
| RadioLib default (LoRa) |
~15-20ms |
~80 kbps |
| Raw SPI bypass (direct LR2021 commands) |
188µs |
838.8 kbps |
| FLRC air rate (theoretical max) |
— |
2600 kbps |
Root cause
RadioLib's RX pipeline performs multiple SPI round-trips per packet:
readData() — read FIFO via RadioLib abstractiongetRSSI() — separate SPI readstandby() — mode change (SPI command + BUSY wait)startReceive() — re-enter RX (SPI command + BUSY wait)
Each round-trip is a CS-low → SPI command → CS-high sequence with a BUSY wait. On a single-core ESP32-C3 at 80 MHz, this adds up to ~15ms per packet.
Raw SPI bypass approach
By accessing LR2021 registers directly (bypassing RadioLib's per-packet methods), we collapse 8+ SPI transactions into 3:
- Read FIFO at offset 0 (single burst read)
- Clear IRQ flags
- Restart RX (no standby needed)
This achieves 838.8 kbps (8.3x improvement) with 500/500 unique packets, 0% PER.
Impact on MeshCore
- LoRa mode (current): No impact. LoRa air time (100ms+) dwarfs processing overhead.
- FLRC mode (future): Significant. If MeshCore adds FLRC support for high-throughput scenarios (file transfer, image sharing), this overhead becomes the bottleneck.
Suggestion
A future setFastRxMode() option in RadioLib could use minimal SPI round-trips for FLRC/high-speed modes. This would benefit any RadioLib user running FLRC, not just MeshCore.
References
This is informational — no action needed unless MeshCore plans FLRC support.
Finding
During LR2021 throughput characterization for the variant PR (#2739), we measured RadioLib's per-packet RX pipeline overhead on ESP32-C3:
Root cause
RadioLib's RX pipeline performs multiple SPI round-trips per packet:
readData()— read FIFO via RadioLib abstractiongetRSSI()— separate SPI readstandby()— mode change (SPI command + BUSY wait)startReceive()— re-enter RX (SPI command + BUSY wait)Each round-trip is a CS-low → SPI command → CS-high sequence with a BUSY wait. On a single-core ESP32-C3 at 80 MHz, this adds up to ~15ms per packet.
Raw SPI bypass approach
By accessing LR2021 registers directly (bypassing RadioLib's per-packet methods), we collapse 8+ SPI transactions into 3:
This achieves 838.8 kbps (8.3x improvement) with 500/500 unique packets, 0% PER.
Impact on MeshCore
Suggestion
A future
setFastRxMode()option in RadioLib could use minimal SPI round-trips for FLRC/high-speed modes. This would benefit any RadioLib user running FLRC, not just MeshCore.References
fast_rx.cppin the same repoThis is informational — no action needed unless MeshCore plans FLRC support.