From dd7f77dba29075c0e35501547ce51c14ff3a185f Mon Sep 17 00:00:00 2001 From: KnightGOKU <162995953+KnightGOKU@users.noreply.github.com> Date: Fri, 4 Sep 2026 18:33:34 +0800 Subject: [PATCH] fix: invalidate dcache when PMP permissions change --- C910_RTL_FACTORY/gen_rtl/cp0/rtl/ct_cp0_regs.v | 16 ++++++++++++---- C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_icc.v | 10 +++++----- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/C910_RTL_FACTORY/gen_rtl/cp0/rtl/ct_cp0_regs.v b/C910_RTL_FACTORY/gen_rtl/cp0/rtl/ct_cp0_regs.v index 11e75188..b4381f64 100644 --- a/C910_RTL_FACTORY/gen_rtl/cp0/rtl/ct_cp0_regs.v +++ b/C910_RTL_FACTORY/gen_rtl/cp0/rtl/ct_cp0_regs.v @@ -1127,7 +1127,7 @@ gated_clk_cell x_cp0_cdata_gated_clk ( .clk_out (cdata_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (cins_r ), + .local_en (cins_r || cp0_pmp_wreg), .module_en (regs_xx_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); @@ -3336,6 +3336,11 @@ begin cdata0[63:0] <= 64'b0; cdata1[63:0] <= 64'b0; end + // Do not retain data captured before a PMP permission change. + else if (cp0_pmp_wreg) begin + cdata0[63:0] <= 64'b0; + cdata1[63:0] <= 64'b0; + end else if (cdata_data_vld) begin cdata0[63:0] <= cdata_read_data[63:0]; cdata1[63:0] <= cdata_read_data[127:64]; @@ -4216,7 +4221,12 @@ assign cp0_lsu_ctc_flush_dis = ctc_flush_dis; // Dcache Clear and Invalid assign cp0_lsu_dcache_clr = clr && sel[1]; -assign cp0_lsu_dcache_inv = dcache_inv && sel[1] || iui_regs_rst_inv_d; +// A PMP update can revoke access to lines already resident in D-cache. Flush +// the cache on every PMP CSR write so cache-index diagnostics cannot read a +// line after its PMP permissions have been tightened. +assign cp0_lsu_dcache_inv = dcache_inv && sel[1] + || iui_regs_rst_inv_d + || cp0_pmp_wreg; // Dcache Read Cache Line Request assign cp0_lsu_dcache_read_req = cins_r && (cindex_rid_dcache_st_tag @@ -4390,5 +4400,3 @@ assign cp0_pad_mstatus[63:0] = mstatus_value[63:0]; // &ModuleEnd; @4181 endmodule - - diff --git a/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_icc.v b/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_icc.v index d8bfce71..9e6b2b93 100644 --- a/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_icc.v +++ b/C910_RTL_FACTORY/gen_rtl/lsu/rtl/ct_lsu_icc.v @@ -264,6 +264,7 @@ assign icc_clk_en = sq_icc_req || cp0_lsu_dcache_inv || cp0_lsu_dcache_clr || cp0_lsu_dcache_read_req + || icc_inv || !icc_idle; // &Instance("gated_clk_cell", "x_lsu_icc_gated_clk"); @48 gated_clk_cell x_lsu_icc_gated_clk ( @@ -422,14 +423,14 @@ assign icc_start = icc_idle && (sq_icc_req || cp0_lsu_dcache_clr || cp0_lsu_dcache_inv - || cp0_lsu_dcache_read_req); + || cp0_lsu_dcache_read_req + || icc_inv); assign icc_set_clr = icc_idle && (sq_icc_req && sq_icc_clr || cp0_lsu_dcache_clr); -assign icc_set_inv = icc_idle - && (sq_icc_req && sq_icc_inv - || cp0_lsu_dcache_inv); +assign icc_set_inv = (icc_idle && sq_icc_req && sq_icc_inv) + || cp0_lsu_dcache_inv; //========================================================== // State 1 : wait for ready @@ -569,4 +570,3 @@ assign lsu_had_icc_state[2:0] = icc_state[2:0]; // &ModuleEnd; @354 endmodule -